Technical Field
Generally, an embodiment relates to packaging and assembly processes of electronic systems including one or more integrated circuits (ICs).
Description of the Related Art
Immense progress has been made in the field of semiconductor production techniques by steadily reducing the critical dimensions of circuit elements, such as transistors, in highly complex integrated circuits. For example, critical dimensions of 30 nm and less have been implemented in highly complex logic circuitry and memory devices, thereby achieving high packing density. Consequently, more and more functions may be integrated into a single semiconductor chip, thereby providing the possibility of forming entire systems on chip so that highly complex electronic circuits may be formed on the basis of a common manufacturing process.
Typically, upon increasing the complexity of an integrated circuit provided on a single semiconductor chip, the input/output (IO) capabilities are also increased in order to address the demands for communication with peripheral circuitry in complex electronic systems. Typically, a semiconductor chip is attached to an appropriate substrate or package, which may impart superior thermal and mechanical integrity to the sensitive semiconductor chip and which may also represent an appropriate interface so as to provide an electrical connection from the integrated circuit to a peripheral electronic component, such as a printed circuit board (PCB), which in turn may have any appropriate configuration so as to represent a part of an overall complex electronic system. Frequently used contact technologies for coupling the semiconductor chip with a package include wire bonding or direct electrical connection of appropriately designed contact structures provided on the semiconductor chip and the package substrate. For example, in the case of direct contact regimes, solder balls, solder bumps, contact pads, or any other appropriate contact elements in the form of metal pillars, and the like, may be provided in appropriate metallization systems of the semiconductor chip and the package in order to establish a reliable electrical and mechanical connection upon attaching the semiconductor chip to the package substrate.
Although the packing density of complex integrated circuits has been significantly increased due to the reduction of the critical dimensions as discussed above, the volumetric packing density of packages has not been increased in a similar proportion, since for higher complexity of the integrated circuits, in which basically a two-dimensional complex arrangement of circuit elements is provided, a corresponding highly complex routing system is typically required in the package so as to finally appropriately couple to a PCB in order to combine the various components of a complex electronic system. In order to increase the volumetric packing density of a package, it has been proposed to provide three-dimensional chip systems, in which two or more semiconductor chips may be provided in a stacked configuration within a single package, thereby significantly increasing the volumetric packing density for a given footprint of the package.
The three-dimensional configuration of the semiconductor chips, however, may require appropriate routing strategies in order to establish electric communication between the individual electronic circuits provided in the various semiconductor chips. Furthermore, generally the complexity of the routing arrangement in the package may also increase in order to provide the required input/output capabilities for coupling the package to other components, such as other packages and external electronic components of the electronic system under consideration. As is well-known, a general electronic system is coupled to the outside world by means of connections/wired channels, such as cables or wires, optical fibers, etc., or by means of wireless channels of an electromagnetic type. Such connections allow for exchanging information signals or supplying power/energy.
At the lowest level of an electronic system, connections of circuit elements within a single semiconductor chip are established by providing conductive lines and an appropriate metallization system including vertical connections, or vias, and horizontal metal lines, where in complex integrated circuits a plurality of metallization layers are stacked in order to provide the electrical connections between the individual circuit elements. The interconnection of the one or more semiconductor chips with a package is typically accomplished by providing appropriately dimensioned and positioned contact pads, for instance, at the last metallization layer of the metallization system of a semiconductor chip, and implementing a wiring system in the package, for instance a contact structure or bond pads that may be coupled to the contact pads of the one or more semiconductor chips. The connections may typically be established on the basis of conductors or metal traces formed in the dielectric material of the package, for instance in or on respective dielectric substrates, within the mold material that typically includes and protects the various components in the package, and the like. Finally, a package contact structure, for instance provided in the form of solder pads, and the like, enables the coupling to an external component, such as a PCB of an electronic system. Typically, the connection to the PCB is achieved at the bottom surface of the package at which the package contact structure is provided.
Due to the increasing complexity of electronic systems, there is a continuous drive in reducing the overall dimensions, for instance of the package of semiconductor devices, in order to increase the total packing density. That is, great efforts are being made in reducing the overall dimensions of the packaged semiconductor device while still providing the required input/output resources so as to couple to the PCB of the electronic system.
For example, U.S. Pat. No. 7,923,290 B2, which is incorporated by reference, is directed to manufacturing techniques that address the demands for increased miniaturization of components, greater packaging density of integrated circuits, superior performance, and reduced costs for complex electronic devices, in particular with respect to portable information and communication devices, such as cellular phones, personal data assistants, camcorders, notebook computers, and the like. For example, a configuration of the type PoP (Package on Package) is suggested and, thus, the area occupied by the package is dominated by the chip with the largest dimensions. The presence of the support structure increases the dimensions of the package. Moreover, in this concept all interconnections are finally rooted to the bottom surface of the lower package for being coupled to a PCB. Furthermore, the routing within the semiconductor chip is implemented on the basis of a TSV (through-silicon via) approach of the “via last” type, which, thus, entails the formation of the vias through the entire IC.
With respect to enhancing packaging of a plurality of semiconductor chips, US Patent Publication 2009/0194887 A1, which is incorporated by reference, discloses a multiple chip package, in which basically two chips are packaged individually, wherein the corresponding packages are appropriately designed so as to allow efficient coupling on the basis of solder bumps, thereby forming a stacked package configuration.
US Patent Publication 2008/0142941 A1, which is incorporated by reference, describes a three-dimensional electronic packaging structure with enhanced grounding performance and embedded antenna, wherein the various packaged semiconductor devices are coupled to each other by means of a corresponding contact structure coupling a bottom surface of one packaged device with the top surface of a further packaged semiconductor device.
US Patent Publication 2011/0024904 A11, which is incorporated by reference, relates to semiconductor packages and to a package-on-package semiconductor device, in which the stacking of packaged semiconductor devices may be enhanced by providing an appropriate electrode unit embedded in the mold material of each of the packages.
US Patent Publication 2011/0227206 A1, which is incorporated by reference, discloses a packaging system with a lead frame for a semiconductor device, wherein a base device in the form of a semiconductor chip is attached to a base substrate, followed by the attachment of a lead frame having a lead-frame pillar adjacent to the semiconductor device. Thereafter, a mold material is applied and partially removed together with a portion of the lead frame in order to partially expose the lead-frame pillar. Also in this case the packaging is enhanced in the vertical direction of the finally obtained package.
Thus, current packaging architectures may be limited due to the fact that the connectivity of the ICs and the package develops in the vertical direction and also the connectivity between packages generally tends to increase in the vertical direction. Indeed, all interconnections are brought to the bottom surface of the package for being coupled to a PCB and, when necessary, some of the interconnections are also routed to the top surface for being coupled to an upper package (PoP).
In other packaging strategies, it is attempted to reduce the lateral area by providing a wiring system in the form of a “lead frame” formed by well-established plating techniques on a permanent or sacrificial substrate, thereby enabling the fabrication of a plurality of contact pads at reduced size and superior accuracy, which in turn may result in increased input/output resources for a given available bottom surface or top surface of a corresponding package. Furthermore, in these manufacturing techniques, a plurality of package substrates may be formed in a single manufacturing process as a continuous block of a plurality of packages, which may be separated after having received the corresponding semiconductor chips and after coupling the chips to the contact pads of the packages.
Consequently, connectivity in the packaging tends to develop generally in a vertical direction, whereas in the PCBs the connectivity tends to increase in complexity in a horizontal direction.